1. Field of the Invention
The present invention generally relates to high speed circuit transceivers, and more particularly to a driver circuit for a high speed circuit transceiver designed to have extremely fast transition speeds and a substantially constant latency for transitions from a logic zero state to a logic one state, and for transitions from a logic one state to a logic zero state.
2. Discussion of the Related Art
Synchronous data systems have long been known. As is known, a synchronous data system is one in which data transfers occur coincident with a clock or some other strobe signal. In this regard, a driver places data on a bus in a known relation to, for example, a clock signal. In accordance with appropriate system design and defined setup and hold times, the driver places the data on the bus with sufficient time for the data to become valid, before the triggering edge of the clock signal. At the triggering edge (either rising edge or falling edge) of the next clock signal, data placed on the bus is clocked into a receiver.
Typically, the clock or other strobe signal is a global one, that extends throughout a system. In this regard, reference is made to FIG. 1, which shows a block diagram of a portion 10 of a synchronous data system as is known in the prior art. A clock generating component 12 (usually a crystal oscillator) provides a periodic alternating waveform 14, such as a square wave, that provide a synchronizing clock signal for all registered components in the system. The signal is carried on a conductor 16 to various components, and may be passed (through cabling, a motherboard backplane, or otherwise) to other circuit boards in the system.
For purposes of illustration, FIG. 1 shows only a few basic circuit components. These include a CPU 18, such as a microprocessor, and several registers 20, 22, 24. As illustrated, the clock signal 14 is routed to each of these components. When data is to be transferred from the CPU 18 to a register 20, or from a register 20 to the CPU 18, it is transferred in a synchronous manner. For simplicity, chip select circuitry and other control circuitry has been omitted from the drawing, but the existence and operation of such circuitry will be known and appreciated by those skilled in the art. For example, each of the registers 20, 22, and 24 will be uniquely address, as determine by the state of an address bus (not shown). Decoder circuitry, controlled by the address bus, then individually enables or selects the registers 20, 22, and 24, based upon the address specified by the address bus.
By way of example, consider a data transfer from the CPU 18 to the register 20. As illustrated by the small circle at the clock input to the register 20, the register 20 of the illustrated embodiment is active on the negative going edge of the clock signal 14. Thus, the CPU 18 must place the data on the data bus 26 at least some time before the negative going edge of the clock 14. As illustrated in FIG. 2, this is referred to as a setup time. In this regard, the data setup time recognizes that a finite period of time is required for data signals to propagate through components in the CPU before reaching their final state. Therefore, the CPU 18 must begin the output process before the negative going edge of the clock 14. Also, the CPU 18 is required to hold the data for a predetermined period of time after the negative going edge of the clock 14 (known as the hold time). The concepts of setup times and hold times in synchronous data systems are well known and need not be further explained herein.
While synchronous data systems of the type described above provide an effective way of communicating data between circuit components in a synchronized fashion, they suffer a number of shortcomings, as the system clock speeds increase. Specifically, in many data systems presently under design, data transfer rates are 250 mega transfers per second (MT/s), and are fast approaching 500 MT/s. In general, speed is extremely important and the faster the system the better. Conventional global clocked systems are incapable of meeting the requirements of transmitting data from chip to chip at these higher data rates, for a number of reasons. Limitations on clocked data I/O pads, clock skew between chips, and bus length are just a few factors that constrain the maximum speed achievable in a conventional global clocked synchronous data system. Indeed, in conventional systems, bus length was not a significant factor in design. However, in a system demanding a 500 MT/s data transfer rate, exchanges must occur in less than two nanoseconds (2xc3x9710xe2x88x929). At these speeds, the delay that may occur along the data path, due in part to bus length, must be a factor for consideration. In fact, the entire manner in which data is communicated must be reconsidered in order to meet the extremely fast data transfer rates desired by present systems.
Accordingly, it is desired to provide a circuit for use in a high data transfer rate system, that effectively addresses and overcomes the shortcomings and concerns of prior art systems.
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the advantages and novel features, the present invention is generally directed to a driver circuit for a high speed transceiver. In accordance with one aspect of the invention, the driver circuit includes a first driver segment disposed to receive a control signal and configured to drive the control signal from a logic zero state to a logic one state and place the driven signal on a first driver segment output. Similarly, the driver circuit includes a second driver segment disposed to receive the control signal and configured to drive the control signal from a logic one state to a logic zero state and place the driven signal on a second driver segment output. In this regard, the control signal is a signal generated internally (i/e., within the chip) to be driven across a bus to another chip. Being relatively weakly driven within the chip, the strength of the control signal must be increased before driving the control signal onto the bus. For this reason, the first driver segment and the second driver segment each include a plurality of drive units that are disposed in a cascaded configuration. As the control signal passes through each successive drive unit, it gains in signal strength. As will be appreciated by persons skilled in the art, this cascaded drive unit configuration provides for an extremely fast overall power build-up of the signals, as opposed to using a single, more powerful drive unit. Furthermore, the cascaded drive units within the first and second driver segments are configured to have substantially the same delay through each.
In accordance with the preferred embodiment of the present invention, the driver circuit is implemented in a high speed transceiver circuit that is used to provide source synchronous data communications. More specifically, the driver circuit is used in a transceiver circuit component that drives both a data signal and a strobe signal that is used by a corresponding transceiver circuit to synchronize the data reception. In such a circuit configuration, it is desirable that the signals (both data and strobe) be driven from low to high states and from high to low states extremely rapidly. For extremely high speed data transfers, not only should the transitions occur very rapidly, but the transition speeds (and timing) should be consistent among the various data bits and the strobe signals. However, the strobe signal will be delayed slightly (preferably by one-fourth of a cycle), either on the transmitter end or the receiver end in order to allow the data bits sufficient time to set up before being read or latched into the receiver.
Further in accordance with the preferred embodiment, the drive units are inverters that are configured with a pair of coupled field effect transistorsxe2x80x94one p-type FET and one n-type FET. Since the same control signal is input to both driver segments, it will be appreciated that one of the driver segments must include an additional inversion. To this end, and in order to generate signals having a desired drive strength at a minimal delay, the first driver segment includes three inverters and the second driver segment includes two inverters. Since it is further desired to maintain a substantially uniform delay between the two driver segments, a non-inverting delay unit is also cascaded within the second driver segment.